NVIDIA Rubin Ultra HBM Downgrade: 12Hi to 8Hi or HBM4

NVIDIA is rethinking the memory configuration for its upcoming Rubin Ultra AI GPU, a shift that directly affects supply availability for data center buyers. The company is moving away from a strict reliance on 12-layer HBM4E memory, which has faced verification delays from major DRAM manufacturers. This strategic pivot aims to stabilize production volumes by offering alternative memory stack designs that are easier to source. Buyers seeking guaranteed unit deliveries may find this flexibility beneficial as the product nears its launch window.

NVIDIA evaluates lower HBM stacks to stabilize Rubin Ultra production volumes

The Rubin Ultra architecture relies heavily on high-bandwidth memory to support its AI workloads, making the memory stack a critical component of its design. Originally, the plan centered on using 12Hi HBM4E modules to maximize bandwidth and capacity. However, NVIDIA is now parallel assessing other solutions to ensure the chip can reach the market. The primary alternative involves reducing the stack height or switching to different HBM generations to mitigate supply chain risks.

• HBM Configuration: Downgraded from 12Hi HBM4E to alternative solutions (HBM4 or 8Hi HBM)
• HBM4E Status: Verification progress has variables; mass production timeline uncertain
• Alternative Strategy: Reduce DRAM Die stack layers to build more HBM stacks, increasing total product shipments under supply constraints

Key technical adjustments include downgrading from the 12Hi HBM4E specification to either HBM4 or an 8Hi stack configuration. Reducing the number of DRAM die layers in each stack allows NVIDIA to produce more complete memory modules from the same amount of raw silicon. This approach increases the total number of Rubin Ultra units that can be assembled despite constraints on overall DRAM supply. The trade-off prioritizes unit volume over maximum per-chip memory capacity.

Industry analysts note that the main performance upgrade for Rubin Ultra lies in its I/O speed rather than raw memory capacity. This makes a reduction in HBM height a viable compromise for many AI training and inference tasks. Some AI ASIC manufacturers are also reportedly considering similar reductions in memory capacity to manage supply constraints. These parallel moves suggest a broader industry shift toward flexible memory configurations during the transition to next-generation standards.

We looked at SK Hynix HBM4 Mass Production Starts in our earlier Nvidia coverage, which highlights the complex timeline for these new memory standards. The current evaluation phase indicates that final specifications are not yet locked in. NVIDIA continues to weigh the benefits of higher capacity against the practicalities of manufacturing yield and supply stability.