CXMT HBM3 Yields Sink to 25% as 80% of Chips Fail Final Tests

CXMT is struggling to produce HBM3 memory chips at a viable scale, with production yields stuck between 25% and 30%. This bottleneck matters because high-bandwidth memory is the primary fuel for AI data centers, and supply constraints here ripple through the entire hardware market. Buyers relying on these chips for high-performance computing face potential delays or reduced availability.

Chinese manufacturer struggles with stacking and bonding processes for AI memory

The Chinese manufacturer is attempting to stack eight layers of DRAM to create its HBM3 modules. This architecture requires precise vertical integration to function, but the current production line is failing to meet quality standards. The firm is attempting to enter a market segment currently dominated by SK hynix, Micron, and Samsung.

A standard CXMT HBM chip contains approximately 3,000 Through Silicon Via (TSV) cutouts that connect the stacked layers. These tiny connections are the primary point of failure during the manufacturing process. The company reports that only 70% of the final products pass additional testing and evaluation after the initial yield loss.

Almost 80 out of every 100 HBM3 chips fail quality clearance in the final stages. This high failure rate indicates significant difficulties in the stacking and bonding processes required for high-density memory. The firm is currently unable to scale production to meet commercial demand.

The exact yield figures are based on industry insider quotes rather than official CXMT data. We looked at earlier HBM production reports while tracking these manufacturing challenges.