Samsung Electronics plans to sample its CXL 3.1 CMM-D memory modules in the third quarter of 2026. Mass production could begin as early as the fourth quarter of the same year, according to a report from THE ELEC.
Doubled per-channel transfer rate
The CMM-D module is based on the CXL 3.1 specification and uses the PCIe 6.0 interface. It doubles the per-channel transfer rate compared to the previous CXL 2.0 standard, delivering greater memory bandwidth.
Samsung will deliver samples to major server and data center customers in Q3 2026. Volume production is targeted for Q4 2026.
CXL memory supports pooling, which allows multiple processors to share a common memory pool. This capability can improve memory utilization and flexibility in data center environments.



Discussion
0 comments
Log in to join the thread with a thoughtful take, question, or correction.