New HBM Stacking Process Quadruples Memory Density for AI Chips

Researchers have developed a manufacturing process that could significantly increase the storage capacity of high bandwidth memory chips used in AI and GPU systems. This advancement matters because it allows more data to be packed into the same physical space, which helps solve the bottleneck where memory speed limits processor performance. The method enables stacking more than ten ultra-thin chip layers, effectively quadrupling the integration density compared to current commercial standards.

Researchers combine transfer printing and bonding to stack ultra-thin layers

The technology comes from the Korea Institute of Industrial Technology and Pohang University of Science and Technology. They combined transfer printing with in-situ bonding to handle chips that are only about 14 micrometers thick. This approach allows them to stack approximately four times more layers than traditional 12-layer HBM structures within the same vertical space.

• Stacking Layers: Over 10 layers
• Integration Density Increase: Approximately 4 times that of commercial HBM
• Chip Thickness: Approximately 14 micrometers
• Processing Temperature: Below 180°C
• Processing Pressure: Below 20,000 Pascals

The fabrication process operates under gentle conditions to protect the delicate silicon layers. It runs at temperatures below 180 degrees Celsius and pressures under 20,000 Pascals. These low-stress parameters help suppress structural warping and keep alignment errors between layers extremely small.

This research breakthrough targets the growing demand for faster memory in artificial intelligence applications. The new process directly addresses the physical limits of current memory packaging by increasing vertical density. If successfully commercialized, this method could allow future AI accelerators to access significantly more data without increasing their physical footprint.

The technology remains in the research phase and is not yet available for commercial purchase. No pricing or availability dates have been announced for this specific stacking method. The researchers confirmed the technical feasibility of the process but did not provide a timeline for mass production or integration into consumer hardware.