AMD EPYC Venice and Verano CPUs: Zen 6 Architecture, Up to 256 Cores and 512 Threads

AMD announced the EPYC Venice and Verano CPU series for 2026. The new processors use the Zen 6 and Zen 6C architectures. These chips aim to increase computing density and I/O capabilities.

The Venice series supports up to 256 cores and 512 threads. The SP7 socket version offers up to 128 PCIe Gen 6.0 lanes plus 16 PCIe Gen 4 lanes. The SP8 socket version provides up to 192 PCIe Gen 6.0 lanes plus 16 PCIe Gen 4 lanes. Memory support reaches 8000 MT/s for ECC and 12800 MT/s for MRDIMM. The Venice Zen 6C model includes 1024MB of total L3 cache. The standard Venice Zen 6 model features 384MB of total L3 cache. Dual I/O dies on the chip handle PCIe Gen 6.0 and CXL 3.1 functions.

The SP7 EPYC Venice models carry a TDP of approximately 600W. The SP8 EPYC Venice models feature a TDP between 350W and 400W. The Venice series is expected to launch globally in 2026. The EPYC Verano series will follow in 2027 as a Zen 6-based CPU with enhanced price competitiveness.

Zen 6 processors feature 256 cores, 16-channel DDR5, and PCIe Gen 6.0 support

EPYC Venice and Verano CPU Series Specifications

AMD states that these processors raise the bar for core count, computing performance, and I/O capabilities. The Venice lineup introduces dual I/O dies to support higher bandwidth requirements. The SP8 variant delivers more Gen 6.0 lanes than the SP7 variant despite having fewer memory channels. The SP7 platform supports 16-channel DDR5 DRAM. The SP8 platform supports 8-channel DDR5 DRAM. The Venice Zen 6C configuration maximizes cache density across its CCDs. The Venice Zen 6 configuration balances core count with L3 memory allocation.

Source: wccftech.com