Samsung HBM5 to use 2nm base die, targets 50% speed boost over HBM4E

Samsung is advancing its high-bandwidth memory roadmap with HBM5, a move that directly impacts the performance ceiling for next-generation AI accelerators. System integrators and buyers should monitor this development as increased memory bandwidth becomes a critical factor for large language model training and inference. This transition represents a significant advancement toward higher compute density in data centers.

Samsung plans 2nm base die with GAA transistors for HBM5

The new HBM5 architecture relies on a redesigned base die built using Samsung's 2nm process technology. This represents a major leap from the current HBM4 base dies, which utilize a mature 4nm process node. Samsung plans to integrate Gate-All-Around (GAA) transistor structures into this 2nm base die to improve power efficiency and switching speeds.

HBM5 Specifications

• Process Node: 2nm
• Speed Increase Target: 50% over HBM4E
• Transistor Structure: GAA (Gate-All-Around)
• Current Base Die Node: 4nm

Samsung targets a speed increase of over 50% for HBM5 compared to the existing HBM4E standard. Realizing this performance improvement relies on the enhanced transistor control offered by the GAA structure at the 2nm node. The company emphasizes a turnkey advantage by combining its memory design, foundry manufacturing, and advanced packaging capabilities to deliver this chip.

We have been tracking HBM5 closely and previously covered the Furiosa AI Stork, which uses HBM4 memory on a 2nm chip to target lower costs per token. Samsung's adoption of 2nm base dies for HBM5 aligns with broader industry trends focused on higher performance per watt. The company aims to leverage its vertical integration to streamline production of these complex memory stacks.

Samsung has confirmed the technical specifications for the HBM5 base die, including the 2nm process and GAA structure. The target performance metric remains a 50% speed increase over HBM4E. These specifications establish a clear technical baseline for the next generation of high-bandwidth memory products.