SK Hynix HBM4 Roadmap: 48GB Stacks, 40% Efficiency Gain

SK Hynix has unveiled a new roadmap for High-Bandwidth Memory that shifts the industry toward advanced packaging and higher density. This development is significant because AI accelerators and high-end graphics cards depend on memory bandwidth to prevent performance bottlenecks. The company presented these details at Hot Chips 2026 to show how it plans to scale capacity beyond current limits.

SK Hynix details HBM4 specs and hybrid bonding packaging at Hot Chips 2026

The announcement covers two main memory generations: HBM3E and the upcoming HBM4. HBM3E stacks can reach 144GB of capacity while delivering 4TB/s of bandwidth. This performance fits into half the physical space required by standard GDDR6 memory. HBM4 targets a maximum capacity of 48GB per stack with 2,048GB/s bandwidth.

SK Hynix is introducing hybrid bonding to enable more than 16 layers of stacking. This technique reduces thermal resistance by 35% compared to the MR-MUF method used previously. The company also plans to increase core die thickness by 24% and shrink TSV pitch to under 18 micrometers. These changes allow for denser and cooler memory structures.

HBM4 improves power efficiency by more than 40% and lowers thermal resistance by 14% compared to HBM3E. The I/O speed for HBM4 reaches 8Gbps. SK Hynix is also developing I-HBM technology to cut thermal resistance by an additional 30% through integrated cooling. Jaesik Lee, SVP of Package Engineering, stated the company uses Intel EMIB for 2.5D packaging and aims for 3D integration next.

We have been tracking HBM (High-Bandwidth Memory) closely, including our earlier coverage on the NVIDIA Rubin Ultra HBM Downgrade. SK Hynix confirmed it is exploring a joint venture with Intel in the memory field, though this remains a rumor. The company is currently utilizing advanced packaging to bridge the gap toward full 3D integration.

SK Hynix has outlined specific technical targets for HBM4 capacity, bandwidth, and thermal management. The roadmap includes hybrid bonding and I-HBM cooling to support future AI hardware demands. These specifications establish the foundation for the next generation of memory infrastructure in data centers and workstations.