JEDEC Announces DDR5 MRDIMM Gen 2 Standard with 12800 MT/s Target

JEDEC announced progress on the development of second-generation DDR5 Multi-Rank Data Buffer (MRDIMM) standards on April 30, 2024. The organization released the formal specification for DDR5 MDB02, designated as JESD82-552. This standard defines the architecture for Multi-Rank Data Buffer modules. JEDEC also previewed the JESD82-542 standard, which covers the Multi-Rank Command/Address Data Buffer (MRCD) specifications. These releases mark significant steps in finalizing the underlying logic for next-generation memory interfaces.

The Gen 2 MRDIMM standard targets a data rate of 12800 MT/s. JEDEC states that the underlying memory interface logic is nearing finalization for this speed. The architecture combines both MDB and MRCD technologies to support higher data transfer rates. This design aims to meet the high bandwidth demands of enterprise servers and artificial intelligence computing workloads. The combination of these buffers allows for more efficient data handling in high-performance environments.

JEDEC releases MDB02 spec and previews MRCD02 for high-bandwidth computing

JEDEC initiated development on the third-generation MRDIMM standard alongside the Gen 2 announcements. The organization continues to refine the specifications to support future computing needs. The focus remains on enhancing memory bandwidth and reliability for data center applications. Industry stakeholders will monitor the finalization of the Gen 2 logic to determine production timelines.

Specifications

• Target Data Rate: 12800 MT/s
• Standard: JESD82-552 (DDR5 MDB02)
• Architecture: Multi-Rank Data Buffer (MDB) and Multi-Rank Command/Address Data Buffer (MRCD)

The release of JESD82-552 and the preview of JESD82-542 provide a clearer roadmap for DDR5 memory evolution. These standards address the growing requirements for data throughput in modern computing infrastructure. JEDEC's work on both Gen 2 and Gen 3 specifications highlights the ongoing effort to improve server memory performance. The industry awaits further updates on the completion of the Gen 2 standard and subsequent module availability.