Intel HB3DM Memory: Z-Angle Stacked Design Targets HBM4 Bandwidth

Intel and Saimemory are developing a new high-bandwidth memory solution named HB3DM. The technology will be presented at the VLSI 2026 conference in June 2026. This announcement marks a significant step in the development of alternative memory architectures for high-performance computing.

The HB3DM module utilizes Z-Angle Memory technology to stack nine layers. The bottom layer contains logic circuitry to manage data movement. Eight DRAM layers sit above the logic layer to provide storage capacity. Each module delivers a total capacity of 10GB. This capacity is distributed as 1.125GB per layer.

Intel and Saimemory unveil a new 10GB module using Z-Angle Memory technology

Intel claims the design achieves approximately 0.25TB/s of bandwidth density per square millimeter. A single module supports a total bandwidth of roughly 5.3TB/s. The architecture uses hybrid bonding with about 13,700 through-silicon vias per layer. The die area for the 10GB module measures 171 square millimeters.

These specifications allow HB3DM to offer significantly higher bandwidth than the competing HBM4 standard. HBM4 provides approximately 2TB/s per stack. Intel states that HB3DM exceeds the speed of HBM4 by a wide margin. The development of HB3DM aims to address the growing memory bandwidth demands of modern hardware.

Specifications

• Architecture: Z-Angle Memory (ZAM) with 9 layers
• Capacity: 10GB per module
• Total Bandwidth: ~5.3TB/s per module
• Bandwidth Density: ~0.25TB/s per mm²
• Die Area: 171mm²

Details regarding the release date and the DRAM manufacturer remain undisclosed. Intel and Saimemory have not yet confirmed which company will produce the base DRAM. Information about the specific production process node is also currently unavailable. These manufacturing details are not yet public.