Intel EMIB-T Scaling to 120x180mm Packages by 2028 for AI

Intel is pushing the boundaries of AI and high-performance computing hardware with a new packaging technology called EMIB-T. This advancement matters because it allows engineers to build significantly larger processor complexes by connecting multiple chiplets into a single, unified unit. By overcoming the physical limits of single-chip manufacturing, this approach enables the creation of AI accelerators that are far more powerful than current generation hardware.

Intel demonstrates advanced packaging for larger AI accelerators

Intel presented the EMIB-T technology at the IEEE 2026 Electronic Components and Technology Conference (ECTC). The company demonstrated that this packaging method can scale to more than eight times the size of a standard reticle die within a 120×120 mm package. This current demonstration serves as a proof of concept for the larger scaling targets Intel has set for the near future.

The technical core of EMIB-T involves scaling the First Layer Interconnect bump pitch down to 25 micrometers. This dense interconnect allows for reliable high-speed signaling that exceeds 12 Gb/s for HBM4e DRAM. Intel also integrated Through-Silicon Vias (TSVs) to handle power routing, which distinguishes this technology from the earlier EMIB-M approach that relied on MIM capacitors.

Looking ahead, Intel plans to scale EMIB-T to more than twelve times the reticle size by 2028. These future packages will measure over 120×180 mm and house more than 24 HBM dies connected by over 38 EMIB-T bridges. This scaling enables ultra-large die complexes with over ten times the number of reticle dies, addressing the growing demand for massive AI model training capabilities.

Intel's EMIB-T technology represents a concrete step toward overcoming the physical scaling limits of traditional semiconductor manufacturing. The demonstration at IEEE 2026 confirms that high-speed signaling and dense interconnects are viable for next-generation AI hardware. This development provides a clear pathway for building the ultra-large die complexes required for future high-performance computing systems.