Astera Labs Leo 2 Memory Controller Launches With 62% AI Speedup

Astera Labs has launched the Leo 2 memory controller series to address the growing memory bottleneck in AI inference workloads. This update matters because it allows data centers to significantly reduce latency for generative AI models without replacing their entire server infrastructure. The new chips enable faster response times for large language models by optimizing how memory connects to processors.

Leo 2 controllers double memory channels to four and support CXL 3.2

The Leo 2 lineup includes the E-Series, P-Series, and X-Series, each targeting different server configurations. The X-Series allows memory expanders to connect directly to AI accelerator fabrics, effectively bypassing the host CPU to reduce latency. Meanwhile, the P-Series introduces memory pooling and sharing capabilities for dynamic resource allocation between host machines. These designs give system builders flexible options for scaling AI clusters.

Specifications

• Memory Channels: 4
• Max DDR5 Capacity: 4TB
• Max DDR4 Capacity: 768GB
• Supported Protocols: PCIe 6.0, CXL 3.2
• Legacy Support: Single-channel 3-slot design, accepts 12 DDR4 sticks

Each Leo 2 controller doubles the memory channels to four, supporting up to 4TB of DDR5 memory or 768GB of DDR4 per chip. The chips are the first to support both PCIe 6.0 and CXL 3.2 interconnect protocols. This dual-protocol support ensures compatibility with the latest high-speed standards while maintaining forward-looking architecture. The increased channel count directly translates to higher bandwidth for data-intensive tasks.

Benchmarking against PCIe-based NVIDIA H200 systems shows the Leo X-Series can reduce Time to First Token by up to 62%. The same configuration also increases token throughput by 22%, which improves the speed of AI inference responses. Astera Labs claims these metrics represent a 62% overall AI inference speedup compared to traditional setups. These performance gains are critical for applications requiring real-time language processing.

Astera Labs stated, "Memory interconnect chip giant Astera Labs recently unveiled its latest technology roadmap, officially launching the Leo series memory controllers supporting the CXL 3.2 interconnect protocol." The company has already begun providing sample chips to leading cloud vendors globally. This early distribution phase signals that production readiness is advancing for enterprise adopters.

We looked at Samsung MD310 CXL 3.2 Memory Module earlier while tracking Astera labs launches. Both products highlight the industry shift toward CXL-based memory expansion for AI workloads. The Leo 2 controllers offer a different approach by focusing on the controller logic rather than just the memory modules themselves.

The Leo 2 series also supports legacy DDR4 via a single-channel 3-slot design that accepts 12 sticks. This feature allows data centers to recycle memory from retired servers, reducing hardware costs. The combination of new high-speed protocols and legacy support makes the Leo 2 adaptable for various infrastructure stages.