The PCI-SIG organization released the version 0.5 draft specification for the PCIe 8.0 standard on May 22, 2024. This release marks a significant milestone in interconnect technology development. The draft specification establishes the foundational architecture for the next generation of high-speed data transfer.
Draft specification establishes foundational architecture for next generation high-speed data transfer
The new standard targets a transfer rate of 256 GT/s. This speed enables up to 1 TB/s of bi-directional bandwidth in an x16 configuration. To achieve this performance, the specification utilizes PAM4 signaling combined with forward error correction and Flit Mode encoding. The design also hits a 0.5V voltage milestone to manage power and signal integrity.
Hardware designers including AMD, Intel, and Nvidia can begin early prototyping based on this draft. The industry is currently evaluating new connector technology to address signal integrity constraints at these high speeds. Final ratification of the specification is expected in 2028, though this timeline remains subject to change.
PCIe 8.0 achieves a data transfer rate that no copper-based standard has ever reached. This leap in performance supports the increasing demands of AI data center computing. The standard represents a major shift in hardware infrastructure capabilities for future systems.
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