TSMC Updates SoIC Roadmap: 4.5 Micron Pitch Targeted for 2029

TSMC updated its system-on-integrated-chip roadmap during a technical seminar in North America on April 30, 2024. The company outlined a clear progression for its interconnect pitch technology. TSMC achieved a 9-micrometer pitch in 2023. The manufacturer plans to reduce this distance to 6 micrometers by 2025. The roadmap targets a further reduction to 4.5 micrometers by 2029. TSMC has not confirmed the exact release date for this 2029 target.

The update highlights significant gains in signal density for face-to-face stacking. This method allows for 14,000 connections per square millimeter. In contrast, face-to-back stacking offers only 1,500 connections per square millimeter. TSMC states that face-to-face stacking enables chip-to-chip communication performance close to on-die interconnect levels. This density increase supports the integration of complex processor designs.

Face-to-face stacking achieves 14,000 connections per square millimeter

Fujitsu's Monaka CPU serves as a primary example of this technology in action. The processor utilizes 144 Armv9 cores for its compute modules. TSMC manufactures these compute modules using its N2 process node. The system also incorporates SRAM chips built on the N5 process node. This hybrid approach combines advanced logic and memory technologies.

The Monaka processor demonstrates the practical application of TSMC's advanced packaging. The use of N2 and N5 nodes alongside SoIC stacking addresses performance demands. The company continues to refine its interconnect capabilities to support future high-density designs. This roadmap update signals a shift toward tighter integration in semiconductor manufacturing.

TSMC SoIC Interconnect Pitch Roadmap

TSMC's focus on reducing interconnect pitch aims to overcome current bandwidth limitations. The transition from 9 micrometers to 4.5 micrometers represents a major engineering milestone. The company relies on face-to-face stacking to maintain signal integrity at these scales. This strategy supports the development of next-generation high-performance computing chips.