CyanSemi launched a new PCIe Gen5 retimer chip on May 29. The LBG5016 aims to solve signal integrity problems in high-speed data centers. It matters because PCIe Gen5 links often struggle with distance and signal loss.
Chip supports x2 to x16 lane configurations
The LBG5016 is a retimer chip that regenerates PCIe signals. It supports lane configurations of x2, x4, x8, and x16. The chip works with both copper and optical cables.
Specifications
- PCIe Generation: Gen5
- Lane Configurations: x2/x4/x8/x16
- Signal Compensation: 36dB at 32GT/s
- Latency: 50% of PCIe Gen5 spec
- Core: RISC-V
At 32 GT/s, the chip provides 36 dB of signal compensation. This doubles the effective transmission distance compared to standard retimers. Latency is only 50% of the PCIe Gen5 specification requirement. The low latency meets CXL cache coherence demands.
Built-in RISC-V core enables programmability
The chip includes a built-in RISC-V core. This core handles timing and voltage margin adjustments. In tests, a copper-optical parallel solution achieved 200 meters of transmission distance.
CyanSemi did not disclose pricing or availability. The chip targets enterprise networking and data center applications. It competes with other PCIe Gen5 retimer solutions.
The LBG5016 is confirmed as a PCIe Gen5 retimer with 36 dB compensation and sub-spec latency. It supports flexible lane bifurcation and extended reach. The RISC-V core adds programmability for system tuning.



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