CAS Institute Unveils 4-Layer Stacked IGZO 3D DRAM Prototype

Researchers from the Chinese Academy of Sciences have developed a 4- layer stacked IGZO 3D DRAM prototype achieving 3 bits per cell density and 400s data retention.

CAS Institute Unveils 4-Layer Stacked IGZO 3D DRAM Prototype

Researchers from the Chinese Academy of Sciences have developed a new memory architecture that could reshape how high-density storage is built. The Institute of Microelectronics and the Beijing Superstring Memory Research Institute created a four-layer stacked 3D DRAM using indium gallium zinc oxide. This design offers higher capacity and bandwidth than traditional static RAM or external dynamic RAM. Buyers interested in next-generation memory components should note that this breakthrough addresses long-standing physical limits in current storage technologies.

Institute of Microelectronics achieves record storage density with new architecture

The core of this innovation is a 2T0C, or two-transistor zero-capacitor, storage unit built on IGZO technology. The team implemented a vertical word line structure with a dual-gate cell design to improve signal stability. This approach allows the memory to maintain high read margins while keeping preparation costs low. The architecture differs significantly from conventional DRAM by eliminating the need for individual capacitors in each cell.

Specifications

  • Architecture: 4-layer stacked 3D 2T0C IGZO DRAM
  • Storage Density: 3 bits per cell
  • Data Retention: 400 seconds
  • Publication Venue: VLSI 2026

The prototype achieves a storage density of three bits per cell, which is a record for this type of architecture. Data retention capabilities reach 400 seconds, providing a stable window for information storage. The research team reports that the device supports high-speed writing operations alongside its long retention times. These technical specifications demonstrate a significant increase in storage density compared to earlier IGZO memory trials.

The research paper detailing these findings is titled 'Highly stackable 3D DRAM of Dual-gate IGZO 2T0C with Record 3 bits/cell and 400s Data Retention.' The work has been accepted for publication at the VLSI 2026 conference. The announcement of this achievement was reported on June 20, 2024. The specific timeline for commercial availability remains undefined in the current reports.

Discussion

0 comments

Log in to join the thread with a thoughtful take, question, or correction.

Add to the discussion