AMD Zen 6 to feature three distinct core types including new Low Power cores

AMD has submitted new Linux kernel patches that reveal the internal architecture of its upcoming Zen 6 client processors. This disclosure matters because it confirms the company is moving away from a uniform core design to a mixed architecture that prioritizes power efficiency alongside raw speed. Buyers and enthusiasts can now see exactly how AMD plans to balance performance and battery life in future desktop and laptop chips.

Kernel patches reveal mixed architecture with dedicated low power tier

The Zen 6 architecture introduces three distinct core types for the first time on client platforms. These include standard Performance cores, Efficiency cores, and a new category called Low Power cores. This third tier is designed specifically to handle background tasks and idle workloads without consuming significant energy. The split allows the processor to dedicate high-speed cores to demanding applications while keeping the system responsive and cool.

Kernel code details show specific changes to the Energy Performance Preference (EPP) values to manage these new cores. The EPP value for Performance cores has increased from 64 to 115 to favor power saving. Meanwhile, the Low Power cores have been tuned for better performance with a balance value raised to 64. Their raw power value was lowered from 115 to 64 to reflect their specialized role in the chip.

Core count configurations vary significantly across the Zen 6 lineup based on the patch data. Mid-range models are expected to use a 10-core arrangement consisting of four Performance cores, four Efficiency cores, and two Low Power cores. High-end models will scale up to a maximum of 22 cores. These patches are scheduled for integration into the Linux 7.4 kernel.

AMD has not released an official launch date for Zen 6 processors. Industry projections suggest the chips will arrive around CES 2027, but this timing relies on the current patch submission schedule. The Linux 7.4 kernel update is expected to land in late 2024 or early 2025, well before the hardware ships. This early software preparation ensures drivers and power management are ready for the new architecture.