AMD has entered mass production of its sixth-generation EPYC server processors, codenamed Venice. The chips utilize TSMC's 2nm manufacturing process. This marks the industry's first high-performance computing product to use this specific node.
Sixth-generation AMD EPYC Venice CPU enters mass production using advanced TSMC 2nm manufacturing process technology.
Venice integrates SoIC-X and CoWoS-L packaging technologies. It also supports LPDDR memory for cloud computing and AI scenarios. AMD states that this support provides higher performance and bandwidth in power-constrained environments.
Spec comparison
| Spec | EPYC Venice |
|---|---|
| Process Node | TSMC 2nm |
| Architecture/Generation | 6th Gen EPYC (Code name: Venice) |
| Packaging Technologies | SoIC-X, CoWoS-L |
| Memory Support | LPDDR memory support |
AMD plans to expand production volume at TSMC's Arizona wafer fab in the future. The company has not provided a specific timeline for this expansion or exact pricing details.
The next-generation Verano platform will also belong to the sixth-generation EPYC series. It focuses on optimizing performance at specific cost and power metrics.
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