TSMC Proposes Three-Layer Cake AI Chip Architecture with COUPE Optical Engine

TSMC has proposed a new AI chip architecture it calls the 'three-layer cake' design. The approach combines compute, heterogeneous integration and 3D IC, and photonics and optical interconnect. The key technology enabling this architecture is COUPE, a compact universal photonic engine.

COUPE micro-ring modulator enters production

The first COUPE product, a 200Gbps micro-ring modulator, entered production in 2025 with a bit error rate below 1e-8. COUPE uses TSMC's SoIC technology to stack an electronic IC and a photonic IC in 3D, improving bandwidth and energy efficiency. TSMC claims COUPE can achieve 4x energy efficiency and 10x latency reduction compared to traditional copper interconnects. With deeper integration into the packaging platform, the company says it can reach up to 10x energy efficiency and 20x latency reduction.

TSMC plans to mass produce COUPE in 2026. The company expects the co-packaged optics market to reach $10 billion by 2030. By that time, TSMC aims to increase bandwidth density 8x to 4TBps using 400Gbps modulators and multi-wavelength and multi-fiber arrays.

Nvidia and Broadcom are adopting COUPE for optical engine connections. TSMC deputy co-COO Zhang Xiaoqiang emphasized the importance of the technology, saying 'You must remember COUPE.' The company has not confirmed the exact launch window for all planned COUPE products.