SpacemiT X200 RISC-V Core Doubles Performance with Xiangshan Kunminghu Architecture

SpacemiT has completed development of its third-generation RISC-V processor core, the X200. The core is based on the Xiangshan Kunminghu architecture and targets cloud computing, agent computers, mini AI supercomputers, and embodied robots.

X200 doubles performance over X100

The X200 achieves a single-core performance of 16 points per GHz on the SPEC2006 Int benchmark, which doubles the performance of its predecessor, the X100. It supports RISC-V Vector and Vector Crypto with a maximum vector length of 1024 bits. The core can operate at up to 3.3 GHz and features a 6-issue, 14-stage pipeline. A single cluster can hold up to 12 cores, and a chip can scale to 128 cores or more. Cluster cache reaches up to 32 MB.

SpacemiT expects the X200 to enter mass production in 2027. The company is already developing the fourth-generation X300 core.

The X200 delivers 50 SPEC2006 Int points per core, according to SpacemiT. The company has not confirmed the exact launch window for the X300.