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Samsung and SK Hynix Compete for 3D DRAM Dominance in AI Era

Samsung and SK Hynix are developing next-generation 3D DRAM manufacturing processes to overcome scaling limits below 10nm. Both companies aim to achieve mass production first and set their solution as the industry standard. Samsung pursues GAAFET process for DRAM Samsung plans to promote a GAAFET process for DRAM, integrating GAAFET transistors with capacitors in the […]

By Mateo Mendoza

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Samsung and SK Hynix Compete for 3D DRAM Dominance in AI Era

and SK Hynix are developing next-generation 3D DRAM manufacturing processes to overcome scaling limits below 10nm. Both companies aim to achieve mass production first and set their solution as the industry standard.

Samsung pursues GAAFET process for DRAM

Samsung plans to promote a GAAFET process for DRAM, integrating GAAFET transistors with capacitors in the same cell. The company is considering a design similar to NAND flash, placing control circuits under the storage array.

Samsung 3D DRAM GAAFET process with control circuits under storage array
Samsung's proposed 3D DRAM design integrates GAAFET transistors and capacitors in the same cell.

SK Hynix adopts 4F2 architecture

SK Hynix has chosen the 4F2 architecture, stacking transistors vertically with gate material wrapping the transistor. The component that receives capacitor data is placed beneath the transistor pillar.

SK Hynix 4F2 architecture with vertical transistor stacking for 3D DRAM
SK Hynix's 4F2 approach stacks transistors vertically with gate material wrapping the transistor.

The competition between Samsung and SK Hynix in 3D DRAM development is driven by the need for memory dominance in the AI era. According to Wccftech, both companies are vying to lead the next phase of DRAM technology.

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