Samsung Showcases World’s First HBM5 Memory at Computex Taipei 2026

Samsung has shown the world's first HBM5 memory at Computex Taipei 2026. This eighth-generation memory targets high-performance computing and AI training workloads. This represents a notable advancement in memory bandwidth for data centers.

Eighth-generation HBM targets AI and HPC workloads.

HBM5 succeeds HBM3 and HBM3E, targeting the increasing requirements of AI and HPC workloads. The memory uses a 2nm base die paired with 1c nm DRAM cells. Samsung expects the technology to reach the market between 2029 and 2031.

Specifications

• Generation: 8th generation HBM
• Manufacturing process: 2nm base die with 1c nm DRAM
• Cooling method: Immersion cooling
• I/O channels: 4096-bit
• Bandwidth per stack: 4 TB/s

Each HBM5 stack offers up to 4 TB/s of bandwidth, a major jump from previous generations. The I/O channel width expands to 4096-bit, enabling higher data throughput. Standard stack height is 16-Hi, meaning 16 DRAM layers per stack.

Immersion cooling addresses thermal demands of next-gen accelerators.

To handle the increased power density, HBM5 adopts immersion cooling technology. This cooling method allows the memory to dissipate high heat loads efficiently. The adoption of immersion cooling addresses the thermal demands of next-generation AI accelerators.

Samsung showcased the memory at Computex, but the product is still years from commercial release. With a 2029-2031 launch window, HBM5 will follow HBM4 and HBM4E in the market. Samsung presents HBM5 as a long-term solution for future AI systems.

The announcement outlines Samsung's roadmap for high-bandwidth memory. HBM5 will deliver 4 TB/s per stack with a 4096-bit interface. Availability is expected between 2029 and 2031.