TSMC CoWoS SiP 2029 Roadmap: 48x Compute Transistor Growth

TSMC announced plans for a next-generation CoWoS SiP in 2026. The company outlined a significant expansion of its advanced packaging capabilities to meet growing AI computing demands. This new architecture aims to support massive increases in both processing power and memory bandwidth. The technology will rely on a combination of advanced logic, SoIC 3D stacking, and CoWoS integration.

The new design will feature a maximum reticle size of 14 or larger. This represents a substantial increase from the standard reticle size of 26mm by 33mm, which covers 858 square millimeters. The interposer for this system will measure 12,020 square millimeters. TSMC plans to support up to 24 HBM5E stacks within this configuration. These specifications enable a projected 48x increase in compute transistors and a 34x increase in memory bandwidth compared to 2024 baselines.

TSMC projects that the cost of this advanced SiP will exceed 10 times that of mid-2020s advanced SiP. The company attributes the bandwidth expansion to several factors. Memory itself provides increased capacity. The transition from HBM3 to HBM4 increases the number of input and output pins. The company also plans to apply advanced logic technology to the base die. This approach allows for data speeds exceeding 10Gb/s, which traditional DRAM cannot achieve. Integrating more HBM stacks per package via CoWoS technology further drives these gains.

Massive AI scaling with 24 HBM stacks and 34x bandwidth gains

TSMC CoWoS SiP Specifications

Global availability for this technology is scheduled for 2029. The expansion of AI computing relies on the integration of high-density components. TSMC stated that higher data speeds, more input and output channels, and increased stacking all contribute to overall bandwidth expansion. TSMC's CoWoS SiP aims to deliver up to 34 times the memory bandwidth of 2024 baseline SiP by 2029.

Source: tomshardware.com