SiFive has announced the Performance P570 Gen 3 CPU IP core. The new core is fully compliant with the RISC-V RVA23 profile. It features a 3-issue, 13-stage out-of-order scalar execution pipeline with a 128-bit VLEN vector pipeline.
P570 Gen 3 verified on TSMC nodes
The P570 Gen 3 has been verified on TSMC 12nm and 3nm process nodes. SiFive claims a 13% IPC improvement over the P550 Gen 1 in SPECint 2017. Dynamic power is reduced by 13% on the 12nm node. Geekbench IPC is doubled for AI workloads. Object detection performance is 21 times that of Gen 1 and 4.5 times that of Gen 2, enabled by dot-product instructions.
SiFive also launched the Performance P550 Gen 3 core for area-constrained designs. The P570 Gen 3 is built to meet demanding consumer and commercial application needs, according to SiFive co-founder and chief architect Krste Asanovic. The core offers world-class RVA23 features and compatibility with all major operating systems.
SiFive has not disclosed pricing or availability for the new IP cores.
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