IBM introduced its first dual-architecture mainframe processor, a move that allows enterprises to run both IBM Z and Arm workloads on the same hardware. This consolidation simplifies infrastructure management by eliminating the need to maintain separate server fleets for different operating systems. Buyers who rely on mainframe reliability but need Arm efficiency can now migrate applications without replacing their core systems.
New 2nm chip allows enterprises to run IBM Z and Arm workloads on same hardware
The new chip targets the IBM Z and LinuxONE platforms, bridging the gap between traditional mainframe computing and modern Arm-based servers. IBM presented the processor at the Hot Chips conference, marking a significant step in its partnership with Arm. The design enables organizations to execute legacy mainframe applications alongside new Arm-native software on a single silicon die.
Specifications
- Process Node: 2nm
- Core Count: 11
- Clock Speed: Over 5.7GHz
- Architecture: IBM Z and Arm
- Integrated Components: AI accelerator, DPU
Built on a 2nm manufacturing process, the processor integrates 11 high-performance cores running at frequencies exceeding 5.7GHz. The architecture includes an on-chip data processing unit (DPU) and a large cache to handle complex data tasks. An integrated AI inference accelerator sits directly on the chip to speed up machine learning workloads without requiring external hardware.
Systems based on this processor can scale to hundreds of cores and tens of terabytes of memory to support massive enterprise workloads. The dual-architecture design allows customers to run both IBM Z and Arm operating systems simultaneously. This capability enables hybrid cloud strategies that combine mainframe security with Arm scalability.
IBM confirmed the technical specifications and architectural capabilities of the new mainframe chip. The announcement establishes a unified hardware foundation for future IBM Z and LinuxONE deployments. Enterprises can now plan infrastructure upgrades that leverage both instruction sets on a single platform.



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